Functional Verification and Testbench Generation

80 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers TO COMPETE IN THE MARKETPLACE, all semiconductor products have tight time-to-market requirements. With design complexity exploding, functional verification is now on the critical path to RTL signoff and relies mainly on extensive vector simulation. A typical microprocessor requires billions of simulation cycles to tape out. But microprocessor manufacturers aren’t the only ones concerned about the increasingly long simulation time. More and more, SoC and ASIC manufacturers face the same challenge. This special issue focuses on the important problem of functional verification and testbench generation for verifying complex digital ICs—a synergistic area that has significant impact on both the test and verification communities. The articles in this issue cover many different aspects of functional verification, including verification methodology, test program generation, case studies, design specification, and model checking. The first article, by Allon Adir et al. (IBM Research Lab, Haifa), presents Genesys-Pro, a second-generation model-based testbench generator for functional verification of uniprocessors and multicore processors. Genesys-Pro, an improved version of its predecessor, Genesys, is currently the main functional verification tool for all IBM processors. In the 1980s, IBM was among the first to develop an automatic test program generator using a biased, random, and dynamic generation scheme, coupled with a traditional expert-system paradigm. This early test program generator was architecture dependent; thus, the need for a generic solution inspired the development of a model-based test generation scheme. A model-based test generator consists of two major components: